Personal computers (PC) are increasingly being called upon to interface with and control sophisticated graphics display systems. Such display systems require extraordinarily fast rates of data exchange with the PC. Nevertheless, most PC's today employ the well known word-at-a-time fetch system which accesses one word per memory cycle. Characteristically, PC memory cycles are some seven or more times slower than a PC's internal register and logic operations.
In graphics applications, serially organized memories are often employed to drive display units. Such memories store words end-to-end which words are serially accessed in a raster fashion. If it is desired to transfer data from a serially organized memory to a random access memory (RAM) which is bit planar oriented (as are many PC Rams), the usual sequence involves accessing a word from the serial memory; aligning it; and then reading the aligned bits into bit positions in various planes of the bit-planar RAM. This operation usually utilizes one memory cycle per word transfer with an attendant reduction in the PC's effective speed of operation.
Some PC's employ pipelining techniques to increase their processing speed. In essence, the pipeline technique involves a pre-fetching of an instruction or a group of instructions while one set of instructions is being executed. In memory transfers of the nature above described, the advantages gained by pipelining are lost since each word transfer ends with a "jump" instruction. That instruction causes the series of instructions used for a memory transfer to be reexecuted (or for the "loop" to fold back upon itself). The jump instruction "flushes" any pre-fetched instructions which have been pre-accessed and the potential look-ahead benefits are thus lost. One additional problem with a looped instruction structure is that it requires a register to maintain a count of the number of times the loop has been performed. Generally PC registers are in short supply when executing sophisticated graphics display application programs and the use of a count register is to be avoided, if possible.
Accordingly, it is an object of this invention to provide a method for transferring data from a serially organized memory to a bit planar organized memory wherein memory accesses are reduced.
It is a further object of this invention to provide a method for transferring data which is capable of handling plural words at a time.
It is a further object of this invention to provide a method for data transfer which avoids the use of loop instructions.
It is still another object of this invention to provide a method for data unit transfers from a serially organized memory to a bit planar organized memory wherein a translation step is employed which takes advantage of pre-existing relationships between bit positions in the data unit being transferred and bit position in the memory into which the transfer is occurring.